1. Field of the Invention
The present invention relates to an image forming apparatus, and a method and a program for controlling parallel processing, and more particularly, to an image forming apparatus including a CPU (Central Processing Unit) formed with cores, and a method and a program for controlling parallel processing in the image forming apparatus.
2. Description of the Related Art
A CPU having more than one core (called a multi-core CPU or many-core CPU), instead of a CPU having one core, is used as the CPU to be mounted in an image forming apparatus such as an MFP (Multi Function Peripheral) these days. Methods of performing processes with cores include a first method that uses different functions of the respective cores, and a second method that distributes a process among the cores in accordance with the load.
As for the method that uses the functions of the respective cores, JP 2010-226283 A discloses an information processing apparatus that includes: an operation display unit that receives an instruction input concerning an operation and displays various kinds of items; an image processing unit that processes image information; and a processor that includes cores of the same type. In this information processing apparatus, one of the cores of the processor is invariably made to control a process that does not require real-time properties and relates to the operation display unit, and the other one of the cores of the processor is invariably made to control a process that needs to cooperate with the above process and relates to the image processing unit.
By the above mentioned first method, the respective cores execute respective functions. Therefore, some of the cores hardly perform any process depending on the operating condition of the image forming apparatus, and the cores cannot be effectively used. As a result, the processing speed cannot be increased. By the second method, on the other hand, any core is not limited to one function, and accordingly, the cores can be effectively used. However, each of the cores is made to perform various kinds of processes, and therefore, it is difficult to optimize a process.
Processes to be performed by a CPU include a process that requires high speed (or a process that can be performed without communication with any other device such as a sensor), and a process that requires real-time properties (or a process that is performed during communication with some other device such as a sensor). In a case where these processes coexist, if the process that requires high speed is preferentially optimized, process switching such as task switching is not conducted, and a predetermined process is continuously performed. By this method, however, task switching cannot be conducted, and a compound operation cannot be performed. In a case where the process that requires real-time properties is preferentially optimized, the process is performed while task switching is conducted. By this method, however, the task switching is controlled by scheduling of the OS (Operating System), and therefore, a series of processes is suspended from time to time.
That is, in a case where there coexist a process that requires high speed and a process that requires real-time properties, real-time properties in processing cannot be secured if priority is given to the process that requires high speed, and high speed in processing cannot be secured if priority is given to the process that requires real-time properties. As a result, it is not possible to achieve both high speed and real-time properties for the processes.
According to JP 2010-226283 A, control on the process that does not require real-time properties (or requires high speed) is assigned to one of the cores, and control on the process that needs cooperation (or requires real-time properties) is assigned to the other core. By this technique, however, the other core is made to perform only the control on the process that needs cooperation, and the other core is not adequately operated. Therefore, the control on the process that does not require real-time properties cannot be performed at high speed.